With rapid development of a high speed interconnection technology, the transmission rate of a channel has been higher and higher, and has been up to 10 Gbps so far. A signal at a high transmission rate is typically transmitted in the form of a pair of differential signals consisting of two signals with opposite polarities. One of the two signals with opposite polarities is defined as a positive signal P and the other is defined as a negative signal N. Accordingly, two differential signals are transmitted via two channels. In other words, two paths for signal transmission are required. The negative signal is subtracted from the positive signal at a receiving end to obtain the received signal, on which the processing such as level judging is performed subsequently. That is, the signals are received and processed.
Desirably, the two differential signals with opposite polarities arrive at any point along the channel from a transmitting end to a receiving end simultaneously, also at a decider in a chip at the receiving end simultaneously. Therefore, the differential signals are required to have the same transmission delay to ensure the transmission reliability of the signals. As shown in FIG. 1, the intra-pair skew is required to be 0, so that the optimal received signal can be obtained by subtracting one of the pair of differential signals from the other, as shown in FIG. 2.
In practice, however, because the material characteristic of a circuitry board is anisotropic and differential wirings have different lengths, the transmission delays of two differential signals with opposite polarities may be different during the transmission of the differential signals, thus, the intra-pair skew is not 0.
FIG. 3 is a schematic diagram showing the case where the intra-pair skew is not 0. In this case, the received signal obtained from the pair of differential signals is shown in FIG. 4. The signal obtained after the differential transmission as shown in FIG. 4 is not desirable.
Therefore, a larger intra-pair skew leads to a larger jitter at the receiving end, resulting in a severer error in the optimal sampling point for Clock and Data Recover (CDR), which increases the receiving bit error rate at the receiving end and therefore degrades the system performance. Further, for a signal at a higher rate, any degradation may result in a much higher bit error rate and even a malfunction of the entire system.
Accordingly, a method for eliminating intra-pair skew has been proposed, and in the method, the intra-pair skew is eliminated by compensating differential transmission delays of signals P and N. As shown in FIG. 5, a device for eliminating a delay difference includes delay control modules, delay modules, a subtractor, an error generating circuit and a slicer (i.e. a threshold level decider). In the adaptive compensation of the intra-pair skew, an error component is obtained by subtracting a signal after the slicer from a signal before the slicer and inputted respectively to the delay control modules for signals P and N, each of the delay control modules determines a delay control component according to the error component, and the delay modules determine delay adjustment components for signals P and N according to the delay control components and compensate the intra-pair skew caused by channels.
In the process of implementing the present invention, the inventor discovers that the following problems exist in the prior art. The method for eliminating intra-pair skew in the prior art is disadvantageous in that the intra-pair skew between the signals P and N cannot be measured, as a result, the differential transmission delays cannot be adjusted accurately.